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d a t a sh eet preliminary speci?cation file under integrated circuits, ic17 1997 nov 19 integrated circuits PCF5077T power amplifier controller for gsm and pcn systems
1997 nov 19 2 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T features cmos low-voltage, low-power can be used in burst mode with power-down 3-wire serial bus interface with the bus available in power-down mode on-chip ramp generator for 256 different power levels with two dynamic ranges two programmable regulator start conditions (v kick and v home ) programmable analog output voltage limitation ramping speed depending on the 13 mhz system frequency clock for global system for mobile communications (gsm) and personal communications network (pcn) low swing input buffer for the 13 mhz master clock compatible to a large number of different rf power modules programmable temperature matching dual supply concept for analog and digital part no external filter for suppression of clock pulse feed through direct power control with ramping function (control loop can be switched off) on-chip power-on reset for all registers serial bus is compatible to bus systems independent of additional clock pulse after rising edge of strobe signal low operating current consumption ttl compatible interface programmable gain factor for sensor signal at op1 two different voltages for 1 lsb of the burst power digital-to-analog converter (dac) are programmable. quick reference data notes 1. the voltages v dda1 and v ddd must be equal and v dda2 must be either equal or greater than v dda1 =v ddd . 2. v dda1 =v ddd = 3 v and v dda2 = 5 v. the v dd pins are: v dda1 , v dda2 and v ddd . ordering information symbol parameter conditions min. typ. max. unit v ddd digital supply voltage note 1 2.7 3.0 6.0 v v dda1 analog supply voltage 1 note 1 2.7 3.0 6.0 v v dda2 analog supply voltage 2 (for op4) 2.7 5.0 6.0 v i dd(oper)(tot) total operating current on the v dd pins note 2 - 918ma t amb operating ambient temperature - 40 - +85 c type number package name description version PCF5077T ssop16 plastic shrink small outline package; 16 leads; body width 4.4 mm sot369-1
1997 nov 19 3 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T block diagram fig.1 block diagram. handbook, full pagewidth dac8 dac6 sc-adder slope generator - 0.8 - 0.33 + 0.33 100 mv power level register 8-bit v kick register 6-bit v home register 6 + 2-bit limiter register 2-bit df0/1, dc, dr0/1, test serial bus interface df strobe v dda1 v ddd clk data v ssd v dda2 2 9 10 11 12 13 3 16 6 daca daca kicka qrsa kicka qrsa vs bvs rf input (sensor) 1 4 15 14 c5 19.2 pf c2 v int(n) v int(o) c1 voltage control for rf power module r3 r10 4.2 k w r2 1 k w r1 d1 3.5 k w comparator 30 m a band gap hpa + dc r9 2.8 k w r4 8.4 k w r5 5 k w hpa + dc r8 2.8 k w hpa mgk910 v ssa v ref v ref v ref i bias 6 8 analog filter dr0 dr1 c6 4.8 pf c4 10 pf op4 op1 v ref v ref v dda1 v d1 rf-zero + dc PCF5077T 1/6 control clk13 trig pd 8 5 7 input buffer
1997 nov 19 4 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T pinning symbol pin description vs 1 sensor signal input df 2 programmable 3-state output v dda1 3 analog supply voltage 1 bvs 4 buffered sensor signal output trig 5 trigger signal input v ddd 6 digital supply voltage pd 7 power-down input (active low) clk13 8 13 mhz master clock input (low-swing) strobe 9 serial bus strobe signal input clk 10 serial bus clock signal input data 11 serial bus data signal input v ssd 12 digital ground v ssa 13 analog ground v int(o) 14 integrator output v int(n) 15 integrator inverting input v dda2 16 analog supply voltage 2 (for op4) fig.2 pin configuration. handbook, halfpage PCF5077T mgk909 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vs df v dda1 bvs trig v ddd pd clk13 strobe clk data v ssd v ssa v int(o) v int(n) v dda2 functional description general this cmos device integrates operational amplifiers, two digital-to-analog converters and a serial bus interface to implement an integrating-controller (see fig.1). it is designed to control both the power level and the up- and down-ramping of gsm/pcn transmit bursts. the gsm/pcn power-up and power-down ramping curves are generated on-chip, using an internal clock frequency of 2.166 mhz , that is generated internally by dividing the external 13 mhz clock signal by six. generally, the power amplifier is ramped-up after a rising edge on pin trig and ramped-down after a falling edge. the content of the power level register (bits pl7 to pl0) determines which of the 2 256 possible values the top of the burst will have. to match the controller to different power modules and sensors several parameters must be adapted. the following parameters influence the performance of the transmission system: the external capacitor c1 in fig.1 determines the maximum bandwidth of the power control loop, t cy 1 f clk ------ - = ? ?? depending on the highest steepness of the control curve of the power module and on the sensor attenuation. the maximum output voltage at pin v int(o) to protect the power module: the limiting value of v int(o) can be set to 4, 3.3 or 2.55 v, depending on the contents of the limiter register (bits lim1 and lim0). this limiting results in a ringing at v int(o) (typ. 200 mv peak-to-peak value) but it will not be transferred to the antenna because the power module is in saturation. the limiter register bits lim1 and lim0 can be used to switch off the limiter option (see table 5). the home position at v int(o) : the integrator output voltage at home position ( pd = high and trig = low) is programmed by means of the v home register. bits vh5 to vh0 are fed into a 6-bit dac that generates a part of v home . the temperature behaviour of the home position: bits dvh1 and dvh0 can be used to compensate temperature dependencies ( - 2or - 4 mv/k) of the control curves of the power module. this completes the setting of v home . the kick voltage: the 6 bits of the v kick register (vk5 to vk0) determine the differential integrator input voltage just after a ramp-up starting signal is detected.
1997 nov 19 5 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T the register information is written via a 3-wire serial bus (see sections serial bus programming and data format). the output of pin df is for general purpose which can have three different states (low, high and 3-state), depending on the values of bits df0 and df1 in the serial register. dual supply pins are provided for the analog and digital blocks. reset function after switching on the power supply, the on-chip reset is active for maximal 50 m s when the rising slope of v ddd has reached 1.5 0.4 v. during this reset, all controllers are set to the home position and the registers are set to their default values. if the supply voltage drops below the reset threshold a constant reset will appear. operating conditions pd = low the serial bus interface is operating, e.g. all registers can be programmed but no effect will be seen on any pin. the contents of the registers are passed to the rest of the circuit only during power-up and with the 13 mhz master clock applied. if the low-swing input buffer at pin clk13 is switched off, neither the sc-adder nor the slope generator will function. this means that after the chip is powered-up, the outputs have to settle again to the programmed register values. the settling time is dominated by the slow power-up of the band gap of typically 50 m s. when the chip is used in the burst mode, it is important to switch on the PCF5077T before the power module or the rf power. otherwise it is possible that a positive spike at v int(o) will open the power module. a safe value is t on = 200 m s between the switching on of the PCF5077T and the switching on of the power module respectively the next trig (see fig.3). pd = high the whole chip is active. clk13 clocks the internal state machine as well as the sc-adder and slope generator. every change at trig is recognized if the master clock is running. the contents of the serial bus registers are processed. if the master clock is switched off during power-up, the state machine is stopped and the output of the sc-adder and slope generator becomes undefined. nevertheless, by reactivating the master clock, the output of the sc-adder and slope generator will settle to the old values again. the analog integrating controller the analog integrating controller consists of two operational amplifiers (op1 and op4) and a comparator. op1 amplifies the sensor signal and op4 is used to form a differential integrator. the comparator is used to limit the integrator output voltage to the value selected by bits lim1 and lim0 in the limiter register. a (schottky) diode d1 as external rectifier is connected to pin vs. the sc-adder block generates the voltage for the ramping of the power module.the differential integrator integrates the difference of this voltage and the voltage detected at the diode. the integrator output voltage v int(o) is used to control the power amplifier module.
1997 nov 19 6 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T table 1 de?nition of some voltages used in figs 1 and 3 symbol description v ref reference voltage, typically 1.25 v v d1 voltage over the sensor diode d1 v pl voltage determining the power level; it is generated in the switched capacitor (sc)-adder block if switch daca is closed (i.e. if the signal daca is high) v vs voltage at pin vs when rf is rectified by the sensor diode d1 v bvs amplified voltage from pin vs v kick voltage determining the kick level; it is generated in the sc-adder block if switch kicka is closed (i.e. if the signal kicka is high) v home voltage determining the home position voltage; if hpa signal is active, the output of dac6 plus temperature compensation is ampli?ed and appears at the output of op4 (pin v int(o) ) v qrs low voltage at the output of the sc-adder block which causes a ramp-down with a shortened tail if switch qrsa is closed (i.e. if the signal qrsa is high) v rfin input signal to the power ampli?er ramp generation (see fig.3) the circuit is activated with the pd signal going high before time mask as and deactivated after ramping down, e.g. at time gs to hs. for this usual power-down burst mode application in gsm/pcn mobile stations, the rf input power at the power module must be activated between time as and bs (when the home position at v int(o) has already reached its stable value) and deactivated between time gs and hs. this is necessary for many types of power modules to meet the - 70 db margin. a ramp-up is started by a rising edge of the trig signal. the trig signal and all other internal signals are delayed by two clock periods (2t cy ) with respect to the signal at pin trig. the timing diagram shows a possible relationship between the chip timing (time b to g) relative to the gsm-mask (as to hs). however, the user is free to choose the rising and falling edge of trig independently so that the mask is not violated. d escription of the signals starting at a stable home position of v int(o) at time b - 2t cy the integrator output voltage is regulated to the value defined in the v home register. the output of the slope generator is connected to the negative input v int(n) of operational amplifier op4 (v kick is defined by bits vk5 to vk0 in the v kick register). two clock periods after a rising edge on pin trig, the integrator start condition circuitry is turned off and op4 is switched into an integrator configuration (time b). the hpa switches will open (hpa + dc is either hpa switch or dc bit). switch hpa is closed when there is no home position. due to the negative differential input voltage v kick , the integrator output will start to rise. after 18t cy (time c) the output of dac8 is connected to the sc-adder and slope generator block. the input of the 8-bit dac comes from bits pl7 to pl0 in the power level register. the slope generator will generate a smooth curve between the former and the new output value of the sc-adder block. the power amplifier is ramped-up via the integrator in approximately 22t cy . this condition is stable as long as trig remains high. two clock periods after a falling edge at trig the ramp-down is started (time e). the sc-adder output voltage will change to v qrs ( - 100 mv), because daca becomes inactive and qrsa active. this causes a ramp-down with a shortened tail. the slope generator again generates a smooth curve between the new sc-adder output voltage and the old sc-adder output voltage. the slope generator must have reached its final value at 38t cy after the recognized falling edge of trig because the hpa signal is activated again and by that turning the integrator into its home position (time g). the integrator output voltage will be regulated once more to the value defined in the v home register.
1997 nov 19 7 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T (1) t rfon =t on - 12t cy to t on +2t cy . (2) t rfoff = 44t cy to 66t cy . (3) v kick (start integrator) applied to integrator. (4) v pl applied to integrator. (5) v qrs applied to integrator. (6) v home at output of op4. (7) this timing of the rf input power (from the power module) ensures that the - 70 db margin is met, even if the isolation of the power module is bad. fig.3 timing diagram of a typical ramp-up/ramp-down curve. handbook, full pagewidth as bs cs ds es fs gs hs 4 1 1 6 30 70 22t cy 22t cy 22t cy 18t cy 18t cy 22t cy t 1 t 2 (2t cy ) (8t cy ) db 18t cy 38t cy 2t cy 2t cy b c e g t on 200 m s t off 44t cy trig pd kicka hpa qrsa daca rfin rf-zero (1) (3) (4) (5) (6) (7) (2) mgk912
1997 nov 19 8 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T serial bus programming a simple 3-wire unidirectional serial bus is used to program the circuit. the 3 wires are data, clk and strobe. the data sent to the device is loaded in bursts framed by strobe. programming clock edges and their appropriate data bits are ignored until strobe goes active low. the last four address bits are decoded on the active strobe edge. this produces an internal load pulse to store the data in one of the addressed registers. to avoid erroneous circuit operation, the strobe pulse is not allowed during internal data reads by the rest of the circuit. this condition is guaranteed by respecting a minimum strobe pulse width after data transfer. only the last 16 bits serially clocked into the device are retained within the programming register. additional leading bits are ignored, and no check is made on the number of clock pulses. the fully static cmos design uses virtually no current when the bus is inactive. the bus is also programmable during power-down. data format data is entered with the most significant bit (msb) first. the leading 10 bits p15 to p6 are the data field, the following bits p5 and p4 form the subaddress, while the last 4 bits p3 to p0 are the device address field. the PCF5077T uses only one of the available addresses. the format is given in table 2. the correspondence between data and address fields is given in table 3 and the description in table 4. all three registers in table 3 are set to 00h during reset. table 2 programming register format table 3 register bit allocation table 4 description of bits used in table 3 data bits subaddress device address msb lsb p15 p14 to p8 p7 p6 p5 p4 p3 p2 p1 p0 data9 data8 to data2 data1 data0 sadd1 sadd0 add3 add2 add1 add0 data field (d9 to d0) subaddress device address msb lsb p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 vk5 vk4 vk3 vk2 vk1 vk0 lim1 lim0 dc test 0 0 1 0 1 0 vh5 vh4 vh3 vh2 vh1 vh0 dvh1 dvh0 dr1 dr0 0 1 1 0 1 0 pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 df1 df0 1 1 1 0 1 0 bits description vk5 to vk0 6 bits to control the kick voltage in 64 steps vh5 to vh0 6 bits to control the home position voltage in 64 steps pl7 to pl0 8 bits to control the power level in 256 steps lim1 and lim0 2 bits to control the limiter voltage (see table 5) dc direct control with ramping function (control loop is switched off when dc = 1) test test mode (test = 1); must always be set to logic 0 in application dvh1 and dvh0 2 bits to set the temperature coefficient of v home (see table 6) dr1 gain factor of op1 dr0 gain factor for slope generator output df1 enable of the 3-state output on pin df (for df1 = 0, pin df is in 3-state mode) df0 data output on pin df
1997 nov 19 9 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T table 5 limiter voltage table 6 programmable temperature coef?cient of v home note 1. vh = voltage programmed in v home register bits vh5 to vh0 and generated by dac6. limiting values in accordance with the absolute maximum rating system (iec 134). note 1. pulses of 7 v are allowed for less than 100 ms. lim1 lim0 limiter voltage (v) tolerance at t amb =27 c (mv) tolerance at t amb =85 c (mv) 0 0 limiter off -- 0 1 4.00 250 350 1 0 3.30 250 350 1 1 2.55 250 350 dvh1 dvh0 v home (1) 00vh 0.4 mv/k 01vh - 2 mv/k 20% 10vh - 4 mv/k 20% 11v ss symbol parameter min. max. unit v dda1 analog supply voltage 1 - 0.5 +6.0 (1) v v dda2 analog supply voltage 2 - 0.5 +6.0 (1) v v ddd digital supply voltage - 0.5 +6.0 (1) v v i dc input voltage on all pins (except pin vs) - 0.5 v dd + 0.5 v v i(vs) dc input voltage on pin vs - 3.0 v dd + 0.5 v i i(n) dc input current on any signal pin - 10 +10 ma p tot total power dissipation - 83 mw t stg storage temperature - 65 +150 c t amb operating ambient temperature - 40 +85 c
1997 nov 19 10 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T operating characteristics v dda1 ,v dda2 and v ddd =v dd = 2.7 to 6.0 v; v ddd =v dda1 v dda2 ; t amb = - 40 to +85 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit operational ampli?er (op1) v dda1 analog supply voltage 1 2.7 3.0 6.0 v gb gain bandwidth product v dda1 = 3.0 v 2.0 -- mhz g min minimum gain dr1 = 0 - 8.1 - 7.6 - 7.1 db g max maximum gain dr1 = 1 5.9 6.4 6.9 db v offset offset voltage no load at output - 20 0 +20 mv operational ampli?er (op4) v dda2 analog supply voltage 2 2.7 5.0 6 (1) v gb gain bandwidth product c l = 120 pf; v dda2 =5v; note 2 4 -- mhz psrr power supply rejection ratio v dda2 = 5 v, at 217 hz 50 (3) 55 - db sr pos positive slew rate v dda2 = 5 v; note 4 3.5 15 - v/ m s sr neg negative slew rate v dda2 = 5 v; note 4 3.5 6 - v/ m s v offset voltage offset no load at output - 20 0 +20 mv v o(min) minimum output voltage -- 0.3 v v o(max) maximum output voltage 0.85v dda2 -- v i o output current note 5 4.5 -- ma programmability and accuracy of v pl (dac8) at v int(o) inl integral non-linearity - 1.5 10 lsb dnl differential non-linearity - 0.2 1 lsb v o(min) minimum output voltage dc = 1; dr0 = 1; note 6 - 30 - +60 mv v o(max) maximum output voltage dc = 1; dr0 = 0; note 6 2.72 - 3.15 v sts step size dc = 1; dr0 = 1 - 6 - mv dc = 1; dr0 = 0 - 11.7 - mv programmability and accuracy of v kick (dac8) at v int(o) v o(min) minimum output voltage dc = 1; dr0 = 1; note 6 - 50 - +50 mv v o(max) maximum output voltage dc = 1; dr0 = 0; note 6 270 - 400 mv sts step size dc = 1; dr0 = 1 - 2.6 - mv dc = 1; dr0 = 0 - 5.0 - mv
1997 nov 19 11 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T notes 1. pulses of 7 v are allowed for less than 100 ms. 2. minimum specified frequency at t amb =27 c. for t amb =85 c a typical value of 4 mhz is specified. 3. not tested. guaranteed by design. 4. slew rates are measured between 10% and 90% of output voltage with a load of approximately 40 pf to ground. 5. measured with r l = 1.2 k w , c l = 80 pf and v dda2 = 5 v. the voltage drop at the output is less than 20 mv. 6. referred to v home ; nominal operating condition, direct control (dc = 1), v home programmed to 40. 7. the parameter is measured starting from code 4, due to a saturation effect for the first four codes. programmability and accuracy of v home (dac6) at v int(o) inl integral non-linearity note 7 - 1.0 3 lsb dnl differential non-linearity note 7 - 0.2 1 lsb v o(min) minimum output voltage dvh1 = 0; dvh0 = 0 50 - 170 mv v o(max) maximum output voltage dvh1 = 0; dvh0 = 0 1.95 - 2.25 v sts step size - 33 - mv symbol parameter conditions min. typ. max. unit
1997 nov 19 12 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T dc characteristics v dda1 ,v dda2 and v ddd =v dd = 2.7 to 6.0 v; v ddd =v dda1 v dda2 ; t amb = - 40 to +85 c; unless otherwise speci?ed. notes 1. an ac coupling with 33 pf is recommended. 2. tested at nominal working condition (v ddd =v dda1 = 3 v; v dda2 = 5 v). ac coupling = 33 pf. 3. the necessary start-up time t on = 200 m s (see fig.3) between pd and trig is more than t pu . symbol parameter conditions min. typ. max. unit v ddd digital supply voltage 2.7 3.0 6.0 v v dda1 analog supply voltage 1 2.7 3.0 6.0 v v dda2 analog supply voltage 2 2.7 5.0 6.0 v i dd(oper)(tot) total operating current on the v dd pins f clk13 = 13 mhz; see fig.5 - 918ma i dd(idle)(tot) total idle current on the v dd pins pd = low - 420 m a logic inputs (pins trig, strobe, clk and data) i lil low-level input leakage current v il =0v - 5 - +5 m a i lih high-level input leakage current v ih =6v - 5 - +5 m a c i input capacitance - 10 - pf v il low-level input voltage 0 - 0.2v dd v v ih high-level input voltage 0.5v dd - v dd v 3-state output (pin df) v ol low-state output voltage i ol =i oh =3ma -- 0.4 v v oh high-state output voltage i ol =i oh = 3 ma 0.7v dd -- v i lo 3-state output leakage current v df =0tov dd - 5 - +5 m a low-swing master clock input (pin clk13) i ll input leakage current - 5 - +5 m a c i input capacitance - 10 - pf ? z i ? input impedance f clk13 = 13 mhz; note 1 - 5 - k w v i(p - p) input voltage (peak-to-peak value) note 2 0.35 - v dd v sensor input voltage (pin vs) v i(vs) input voltage at pin vs - 3.0 - v dd v band gap i bias bias current (source for d1) v vs =0v; t amb =25 c; tc = - 0.08 m a/k 21 28 35 m a v ref reference voltage t amb =25 c 1.18 1.25 1.32 v tc temperature coef?cient for v ref - 170 - ppm/k t pu power-up time for v ref note 3 - 550 m s power-on reset, threshold voltage v th ; see fig.4 v th threshold voltage t amb =25 c; tc = - 4 mv/k 1.2 1.5 1.8 v t rst reset time -- 50 m s
1997 nov 19 13 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T fig.4 timing diagram for on-chip reset function. handbook, halfpage mgk914 v ddd internal reset v th < t rst t t fig.5 operating current i dd as a function of v dd . handbook, halfpage 3456 8 6 2 0 4 mgk916 i dd (ma) v dd (v) (1) (2) (3) (1) i dda1 . (2) i dda2 . (3) i ddd .
1997 nov 19 14 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T timing characteristics v dda1 ,v dda2 and v ddd = 2.7 to 6.0 v; v ddd =v dda1 v dda2 ; t amb = - 40 to +85 c; unless otherwise speci?ed. symbol parameter min. typ. unit controller timing; see fig.3 t d(trig-b) delay from positive trig edge to time b = 13 6 t cy - 1.0 m s t d(b-c) delay from time b to time c = 18t cy - 8.31 m s t d(trig-e) delay from negative trig edge to time e = 13 6 t cy - 1.0 m s t d(e-g) delay from time e to time g = 38t cy - 17.54 m s serial bus timing; see fig.6 s erial programming clock ( pin clk) t r rise time - 10 ns t f fall time - 10 ns t cy clock period 100 - ns e nable programming ( pin strobe) t start strobe start time to ?rst clock edge 0 - ns t end strobe end time after last clock edge 40 - ns r egister serial input data ( pin data) t su input data to clk set-up time 20 - ns t h input data to clk hold time 20 - ns fig.6 serial bus timing diagram. handbook, full pagewidth t h t start t end t su t cy lsb clk data strobe msb mgk913
1997 nov 19 15 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T application information direct power control with ramping function (dc = 1) the circuit offers a useful feature to control power levels close to the saturation region of the external power module. this flexibility consists in the direct control on the power level by setting bit dc to logic 1. in this condition, the external control loop is switched off by disabling the gain path from op1. the ramping shape of the signal to be transmitted as well as its final level are driven only by the internally generated control signal from the slope generator. in this way transient effects to recover active components from deep saturation are avoided. the relative error on the absolute value of output power is quite limited, as a power amplifier is less sensitive to temperature variation in its saturated region. however, this way of operating may increase the phase error. increased dynamic range the PCF5077T is able to control a dynamic range of 30 dbm by switching the gain factor of the sensor amplifier and the resolution of dac8. this range corresponds to a maximum peak-to-peak voltage of 3 v measured at the sensor diode. figure 7 shows the voltage at the sensor diode (v s ) versus the output power (p) of the power amplifier (pa) with a directional coupler of 20 db attenuation. the maximum voltage of 3 v is reached when the output power is 35 dbm. the sensor voltage for power level lower than 13 dbm, as necessary for gsm phase 2 and dcs1800, is lower than 200 mv. an 8-bit dac would not be sufficient to cover the complete dynamic range. therefore bits dr0 and dr1 are used to switch the power range that can be controlled with the controller (see table 7). r educed voltage steps of power level dac8 (dr0 = 1) the dr0 bit is used to switch resistor r9 (switch dr0 is closed) at the integrator input (op4). the ratio of the dac8 range to the sensor signal voltage is therefore halved and the power corresponding to one lsb of dac8 is reduced by 3 db. with this setting the power module can be controlled more accurately for low output power levels. g ain factor of op1 (dr1) bit dr1 switches (switch dr1 is closed) the ratio of the capacitances at op1. the gain factor for the sensor amplifier is five times higher when dr1 is in high state. when dr1 = 1, the control loop regulates the output power of the pa to a lower power level. a dynamic range of about 10 dbm can be switched by this manner. v s :v peak is the ratio of sensor signal to slope generator output voltage effective at the integrator output (op4). table 7 gain factors additional application information evaluation kits with software and demonstration board are available for the PCF5077T together with philips power modules bgy206, cgy2010, cgy2020 and cgy2021 for gsm and pcn, which will provide help for applications. very little bus traffic is required for the PCF5077T because the ramping curves are generated on-chip. v kick and v home define the start conditions for up-ramping. v pl determines the power levels. trig is the trigger for up and down-ramping. the non-linear behaviour of the control curves of the power modules have a big influence on the loop. start conditions in the flat area of the control curve are critical and need some attention. initially v int(o) will be at the home position. the hpa switches release the regulator. the integrator is moved into the active part of the control curve. this is achieved by integrating v kick . when v int(o) has reached the active region of the control curve the loop is closed and the circuit is able to follow the ramping function generated by a voltage step to the slope generator. the step height v pl determines the power of the transmit burst. down-ramping is started at the slope generator input by a voltage step from v pl back to v qrs . the loop follows the leading function for down-ramping until the rf sensor measures zero. the reason for v qrs is to shorten the tail of the slope. figures 8 and 9 show the results of measurements on the up and down-ramping where ref is the reference level of the power in the time slot, atten is the attenuation of the input instrument for not to destroy the instrument itself, res bw is the resolution bandwidth, vbw is the video bandwidth, center is the carrier frequency for the burst that has been measured and swp is the sweep time used for the measurement. dr1 dr0 v s :v peak 0 0 1:1 0 1 2:1 1 0 5:1 1 1 10:1
1997 nov 19 16 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T a djustment of the home position the 6-bit dac for v home determines the start point of the burst in the time template. curve 2 in fig.8 shows what happens when v home is too low. the burst starts too late and the up-ramping of the power is too steep. the steep up-ramping results in a wide transient spectra. the rf input power shall be switched off when the trig signal is low to keep the - 70 db margin before the burst. the home position has to be adjusted for each mobile phone because of dac tolerances and individual pa characteristics. the temperature coefficients for v home ( - 2 and - 4 mv/k) are used to compensate the temperature shift of the pa control curve. therefore the pa and the controller shall be placed nearby on the printed-circuit board. additionally it has to be considered that the temperature of the pa and PCF5077T are different because the pa heats up itself. software may help to adapt v home to different temperatures. a djustment of v kick after the falling edge of hpa the integrator starts to increase the control voltage up to the position of v kick where the pa should have reached its active region. increasing v kick at high power level makes the up ramping of the burst smoother and improves the transient spectra. v kick must be reduced for low level of v pl to avoid that both voltages become equal. setting v kick to minimum value for the lowest power level can be sufficient. at low power level the burst will start later because of the bend sensor curve (see fig.7). the trigger pulse has to be started up to 3 bits earlier for the lowest power level to avoid that the power is ramped up too late for the first data bits of the burst. l imit for correct down - ramping the maximum rf power that the power module in saturation is able to deliver depends on rf input power, transmit frequency, supply voltage, temperature and load impedance. the maximum v pl must be matched to the worst case output power and then reduced by 1 db when the PCF5077T is used in closed loop mode. curve 2 in fig.9 shows what happens when the pa is driven into saturation. the down-ramping of the power is getting too steep and therefore the transient spectra will be too wide. the 1 db margin is necessary because of the flat pa control curve at high power level. the loop needs more time to reduce the power during the down-ramping and the control voltage increases. the high control voltage forces the power quickly down when the steep region of the control curve is achieved. the steep down-ramping results in a wide transient spectra. fig.7 sensor voltage as a function of output power (diode bat62). handbook, halfpage 35 - 55 015 10 1 10 - 1 10 - 2 mgk915 25 30 10 20 v s (v) p (dbm)
1997 nov 19 17 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T fig.8 power as a function of time; rising edge (behaviour at different worst case home positions of v int(o) ). handbook, full pagewidth mbe718 kick 70 db 30 db 6 db 1 db +4 db +1 db 40 center 902.400 mhz # res bw 300 khz # vbw 300 khz # swp 80 m s 28 log 10 db/ ref 33.4 dbm atten 40 db 18 10 32 12 0 m s (1) highest usable value. (2) lowest usable value. fig.9 power as a function of time; falling edge. handbook, full pagewidth mbe719 center 902.400 mhz # res bw 1.0 mhz # vbw 300 khz # swp 80 m s log 10 db/ ref 34.8 dbm atten 40 db 591 571 561 553 543 m s 6 db 1 2 30 db 70 db (1) correct behaviour. (2) unusable behaviour with wrong v pl value.
1997 nov 19 18 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T application in mobile stations using a directional coupler with 16.5 db attenuation produces a sensor signal between 100 mv and 3 v below the diode forward voltage at pin vs for the pa output power range of 8 to 36 dbm. the sensor voltage of 3 v at pin vs corresponds to the maximum dac output voltage. the power range that can be controlled is therefore not limited by the sensor voltage input vs and higher power levels can be controlled with the control loop switched on. fig.10 application diagram for mobile stations. handbook, full pagewidth PCF5077T 3-wire serial bus 120 pf c1 33 pf c3 rf power amplifier rf c2 8.2 to 39 pf r1 1 k w antenna sensor mgk911 1 vs trig pd clk13 strobe clk data v ssd v ssa v int(o) v int(n) 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 d1
1997 nov 19 19 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T package outline unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.15 0.00 1.4 1.2 0.32 0.20 0.25 0.13 5.30 5.10 4.5 4.3 0.65 6.6 6.2 0.65 0.45 0.48 0.18 10 0 o o 0.13 0.2 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.20 mm maximum per side are not included. 0.75 0.45 1.0 sot369-1 94-04-20 95-02-04 w m q a a 1 a 2 b p d y h e l p q detail x e z e c l v m a x (a ) 3 a 0.25 18 16 9 pin 1 index 0 2.5 5 mm scale ssop16: plastic shrink small outline package; 16 leads; body width 4.4 mm sot369-1 a max. 1.5
1997 nov 19 20 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all ssop packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering is not recommended for ssop packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. even with these conditions, only consider wave soldering ssop packages that have a body width of 4.4 mm, that is ssop16 (sot369-1) or ssop20 (sot266-1) . during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1997 nov 19 21 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1997 nov 19 22 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T notes
1997 nov 19 23 philips semiconductors preliminary speci?cation power ampli?er controller for gsm and pcn systems PCF5077T notes
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